Next-Gen AMD Zen 6: Slaying Latency with 3nm Chiplets

Well-known leaker MLID has recently disclosed several chip design details regarding AMD's Zen 6 architecture for both desktop and laptop platforms. It's important to note that these details specifically exclude the data center EPYC series. While MLID's leaks frequently generate significant buzz, it's still advisable to approach the accuracy of this information with a degree of skepticism.


According to MLID, the desktop version of Zen 6 is codenamed "Olympic Ridge," contradicting previous rumors suggesting "Medusa Ridge." However, the mainstream mobile version is indeed confirmed to be "Medusa Point." Zen 6 will maintain the chiplet design, utilizing a combination of CCDs (Compute Chiplets) and an IOD (Input/Output Die). Notably, the CCDs are expected to advance to a 3nm-class process, highly likely TSMC's N3E node. The IOD, on the other hand, is slated for a 4nm-class upgrade, potentially manufactured by Samsung, with strong indications pointing towards their 4LPP process, incorporating EUV (Extreme Ultraviolet) lithography technology.



Notably, the Zen 6 CCD will, for the first time, upgrade to a 12-core design, with a corresponding increase in L3 cache to 48MB. This implies that we could see mainstream desktop models featuring up to 24 cores. Furthermore, if 64MB of 3D V-Cache is incorporated, the total cache amount could reach an impressive 184MB.

Zen 6 also tackles the issue of high latency between CCDs. The two CCDs will be interconnected via a new low-latency bridge bus, effectively eliminating this persistent bottleneck. Beyond process upgrades, the IOD is also expected to see improvements in its integrated GPU, memory controller, and PCIe capabilities. Memory support is anticipated to extend to DDR5-8000 speeds and potentially even higher. The integrated GPU is likely to be upgraded to the RDNA4 architecture, while PCIe could advance to version 5.0 or offer an increased number of lanes.

The mobile "Medusa Point" variant will also adopt a chiplet design, sharing the same CCD and IOD, although it will be limited to a maximum of 12 cores. The NPU AI engine is also set to receive further enhancements beyond current levels. Specific performance figures are not yet available, but the desktop version is projected to reach 50 TOPS, matching current performance benchmarks.